highly anticipated: While the Zen 3 announcement is within, we are getting some important details ahead of the October announcement for leaked developer documents. While it doesn’t portray the full picture to look at the leaked Zen 3, it suggests that it should be a more robust CPU series for AMD with a lot of generic improvements.
Confidential documents allegedly leaked by Twitter user CyberPunkCat It seems that details have been given about the change to the Zen 3, which will come with the Ryzen 4000 desktop series, which will have the code “Vermeer”.
We know that AMD is unloading the Zen 3’s wrap in October, and the details found in the documents repeat some of the things we already know, while offering bits of new information. The document appears to be a Processor Programming Reference (PPR) for AMD’s family 19h, model 21h B0, which will be the Zen 3. The previous Zen + and Zen 2 architectures belong to the AMD family of 17h with various models and modifications.
AMD usually provides this type of documentation to developers after launch, so it is not privileged information at all. In addition, such developer documents are easily operational – just ask Intel.
The most notable change to the Zen3 is taking place in the CCD / CCX configuration. The Zen3 will continue to use an MCM (multi-chip module), or chiplet design, which will use two CCDs and one I / O. There will be only one CCX per CCD, and this CCX will consist of eight cores capable of running in single-thread mode (1T) or two-thread SMT mode (2T). So, that is 16 total threads per CCX.
This may suggest that the Zen 3 parts will come out at 16 cores, in the same way as the Ryzen 9 3950X. However, we’ll have to wait and see because AMD may well have some tricks up its sleeve.
In addition, AMD is working for its cash subsystem. The CCX will have a total of 32MB L3 cache (as opposed to 16MB per CCX with Zen 2) shared across all eight cores. While the Zen 2 offered 323 L3 cache per CCD, it had to be shared between two different campuses. There is also 512KB of L2 cache per core within CCX for a total of 4MB of L2 cache per CCD.
Interestingly, AMD is also beefing up the Scalable Data Fabric (SDF), the communication backbone of the Infinity fabric responsible for transporting data and concurrency between cores, memory controllers, and other I / O elements. Documents note that SDF can now handle 512GB per DRAM channel. It seems that there may also be some small changes to the scalable control fabric (SCF), which is the second part of the Infinity fabric that primarily handles signaling.
Elsewhere, the Zen3 memory interface appears to have two integrated memory controllers (UMCs) each supporting one DRAM channel and two supporting DIMMs. There will also be support for the DDR4-3200, which was originally supported with Gen2. It is likely that the Zen3 will retain the same features and connectivity for most Fusion Controller Hubs (FCH) as those present in the Zen2.
In addition to some generic clock speed bumps, it seems likely that the Zen 3 will advance AMD’s MCM approach, focusing on improving compatibility and latency under the hood. We fully expect Zen 2 parts as well as a measurable IPC improvement.